FIG. 3(a) shows a cross-section of a prior art MOS transistor, and FIG. 3(b) shows an equivalent circuit thereof.
In the Figures, the reference numeral 1 designates a semiconductor substrate, and the reference numeral 2 designates an element-separating region comprising a thick insulating film. The reference numeral 3 designates a gate insulating film. The reference numeral 4 designates a gate electrode. The reference numerals 5 and 5a designate a source and a drain region. The reference numeral 6 designates a thick insulating film. The reference numeral 7 designates an aluminum wiring.
The gate electrode 4 is conventionally produced of a polycrystalline silicon into which impurities are doped at a high concentration, but it has a sheet resistance of several tens .OMEGA./.quadrature.. As the pattern is fine-patterned, the resistance is increased to a great extent, and recently a gate electrode having a double layer structure of a high melting point metal silicide and a polycrystalline silicon has been used.
On the other hand, the diffusion layer of the source/drain is required to have a shallow junction depth with the increase in the fineness of elements, and this results in the sheet resistance of the diffusion layer increasing to a great extent. For example, in an N+type diffusion layer of about 0.2 .mu.m junction depth, the sheet resistance becomes 50 to 100 .OMEGA./.quadrature., and in a P.sup.+ type diffusion layer of about the same junction depth, the sheet resistance thereof becomes about 100 to 200 .OMEGA./.quadrature., and the parasitic resistances R.sub.s and R.sub.D become a factor obstructing the element property. Furthermore, the diffusion layer of the source/drain requires a fairly large area for the production of a contact hole, and in cases where it is used as a portion of a wiring the parasitic capacitance produced between the diffusional layer and the substrate has a value which cannot be ignored and prevents the enhancement of the element performance.
Furthermore, since the diffusion layer cannot be used as a portion of a wiring due to the increase in resistance of the diffusion layer, wirings having the same structure as that of the aluminum wiring 7 or the gate electrode 4 comprising a high melting point metal silicide must be used for the internal wirings.
In the prior art MOS transistor with such a construction, a contact for connecting the diffusion layer and the internal wirings therefore has to be provided, and in producing the same a fairly large area is required to assure various overlapping preciseness. Furthermore, the number of contacts becomes tremendously large in a large sized integrated circuit, and the fraction of defective contacts affects adversely the yield of the integrated circuit device.